• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention concerns a PC board with laminates for electrical circuits, the PC board comprising at least one carrier (1) and at least one copper surface layer (7), intended to, after the removal of selected parts, e.g. by etching, function as conductors on the PC board. The new thing is that the carrier at least at some parts has a surface roughness of up to mainly the same size as the thickness of the copper layer and that at least at the above named rough parts is arranged a surface levelling layer (5 a,b) between the carrier (1) and the copper layer (7). Further, the invention concerns a method for producing PC board laminate for electrical circuits as above, the laminate comprising a copper layer and a carrier that has a surface roughness of mainly the same size as the thickness of the copper layer. The new thing here is that a layer (5 a,b) of liquid epoxy is applied on the one or those surface parts of the carrier which in the end are to carry a copper layer, that the epoxy layer is dried and hardened, and that copper layers (7) are plated on the epoxy layers (5 a,b).
    公开号:US20010008680A1
    申请号:US09/753,653
    申请日:2001-01-04
    公开日:2001-07-19
    发明作者:Leif Bergstedt；Per Ligander
    申请人:Telefonaktiebolaget LM Ericsson AB；
    IPC主号:H05K3-387
    专利说明:
    [0001] The present invention relates to a printed circuit board made of laminate for electric circuits, comprising at least one carrier layer and at least one surface layer made of copper intended, after the removal of selected portions, for example by etching, to constitute the conductors on the board. The invention also relates to a method for producing printed circuit board laminate of the abovementioned type intended for electric circuits. [0001] BACKGROUND ART
    [0002] Circuit boards with conductors consisting of a copper layer etched into a pattern located on one or both sides of the board or even inside the board are commonly used within the field of electronics. These boards often have a base layer consisting of glass fibre mixed with epoxy. The glass content in these mixtures can vary, but common values are 40-60%. One problem, especially with an advanced degree of miniaturization, is thermal expansion which can result in breakage and contact difficulties. Another problem is surface roughness. If the quantity of glass is increased, the thermal expansion coefficient decreases, but a disadvantage of this is that the surface of the laminate becomes coarser. A secondary consequence of the surface becoming coarser, that is to say being imparted an inferior surface finish, is that, when copper plating is applied, it is not possible to have too thin a copper layer because the conductor pattern is jeopardized by the coarse surface. On the other hand, with a thicker copper layer, it must be borne in mind that etching has to continue until those portions which are to be removed are completely etched through and removed, which means that the pattern cannot be made too fine-meshed because the etching becomes more uneven at the edges as the etching time increases and the risk of defects then increases. There are circuit boards which have a low thermal expansion coefficient but these are in most cases based on cores of metal or ceramics and are relatively expensive. [0002] DISCLOSURE OF INVENTION
    [0003] By means of the present invention, a circuit board has been produced, in which the material makes it possible for the linear expansion due to temperature increases to be reduced considerably, but in which it is still possible to have relatively thin copper layers and thus a fine-meshed pattern with conductor widths as small as 50 μm. The board is still inexpensive in comparison with, for example, the variants with the metal cores. To this end, the invention is characterized in that the carrier layer has, at least in certain portions, been allowed to have a surface roughness of up to essentially the same size as the thickness of the copper layer, and in that, at least in the abovementioned portions, a surface-levelling plane layer is arranged between the carrier layer and the copper layer. The plane layer suitably consists of epoxy and has a thickness which is essentially the same size as the surface roughness of the carrier layer, that is to say is essentially the same thickness as the surface roughness of the carrier layer. In this connection, a carrier layer which contains glass fibre and epoxy can advantageously be used, and good linear expansion properties are achieved if the glass fibre content exceeds 70%. [0003]
    [0004] The epoxy layer levels the surface of the coarse carrier layer and increases the adhesion between the copper and the glass fibre, so that a thinner copper layer can be used on the surface thus smoothed, which in turn results in shorter etching time and less unevenness at the edges of the etching, with the possibility of narrow conductors. [0004]
    [0005] The new method is characterized in that a layer of liquid epoxy is applied to that surface or those surfaces of the carrier layer which has or have a surface roughness of the same order of size as the thickness of the copper layer envisaged and which in the end is or are to carry a copper layer, in that the epoxy layers are dried and hardened, and in that copper layers are plated on top of the epoxy layers. [0005]
    [0006] In the case of those laminates which are to have through-plated holes, it is an advantage if these holes are drilled after application of epoxy but before the copper-plating because it is then possible to obtain a homogeneous copper thickness. [0006] BRIEF DESCRIPTION OF DRAWINGS
    [0007] The invention will be described and explained in greater detail below with reference to the figures shown in the appended drawing, in which [0007]
    [0008] FIG. 1 shows in cross section a part of a circuit board laminate of what is known as the multilayer type without surface material applied, [0008]
    [0009] FIG. 2 shows the laminate from FIG. 1 with epoxy layers applied, [0009]
    [0010] FIG. 3 shows the laminate with a drilled hole, [0010]
    [0011] FIG. 4 shows the laminate with copper plating applied, and [0011]
    [0012] FIG. 5 shows the laminate after etching has been carried out. [0012] MODE FOR CARRYING OUT THE INVENTION
    [0013] With reference to FIG. 1, the invention includes a laminate [0013] 1 made of glass fibre-filled epoxy. Included in the glass fibre laminate are two inner conductor layers 2 and 3. The conductor layer 2 is provided with an insulating hole 4 for subsequent drilling through without contact. The percentage of glass fibre/epoxy in the glass fibre layer is suitably 75/25, but glass contents as low as 70% are possible. With this high glass fibre content, a linear expansion coefficient as low as 9-10 ppm/° C. is achieved, which is to be compared with the more usual 16-18 ppm for conventionally used circuit board laminates with glass fibre contents of 40-60%. A low linear expansion coefficient is desirable when the copper layer is thin, down towards 18-20 μm, which is in turn the case when it is necessary to etch narrow conductors on account of an advanced degree of miniaturization. It is well known that etching narrow conductors requires a thin copper layer. However, with the abovementioned glass contents, the surface becomes considerably coarser, compared with the conventional laminates, and it is therefore not possible for the desired thickness of copper layer to be applied without encountering problems associated with reliable subsequent pattern-etching in the copper. In order to overcome these problems, according to the invention, a layer 5 of liquid epoxy is applied, as shown in FIG. 2, which is suitably roughly 5-15 μm thick, depending on the surface roughness of the carrier layer, and is dried and hardened. The epoxy can be applied by, for example, rolling, spraying, screening or curtain-coating. The epoxy layer spreads and forms a plane surface outside the uneven surface of the carrier layer, the surface roughness of which, with glass fibre contents of this type, can usually be up to RA±10 μm, and is moreover an excellent base with very good adhesion to the copper. In the figure, the “coarse” surface of the carrier layer is not visible because the surface roughness is exceedingly small in relation to the thickness of the carrier layer 1, while the thickness of the surface-levelling plane layer of epoxy has been greatly exaggerated in order that the layer be included in the figure. As the surface roughness, with glass contents such as these, is up to an RA number of ±10 μm, the thickness of the epoxy layer 5 should therefore be roughly 20 μm in this case. The plane layer of epoxy should not be thicker so as to avoid undesirable effects such as thermal expansion, although the value is not critical. If the circuit board has a double-sided pattern, epoxy is applied to both sides 5 a and 5 b. After this, it would be possible to plate the board so as to obtain an etchable copper layer, but, if the board is to have through-plated holes for transferring contact between the different conductor pattern layers of the board, it is advantageous to drill the holes to be plated before the copper-plating is carried out, because a further plating of the holes afterwards would result in a copper layer of essentially twice the thickness on the surface, which is unnecessary and of course what, inter alia, is to be avoided. FIG. 3 shows how a hole 6 has been drilled through the board in the centre of the insulating hole 4, the drilled hole having a smaller diameter than the insulating hole so that contact cannot be made with the plating to be applied, while the drilled hole penetrates the layer 3 which is to be in contact with the hole plating.
    [0014] When the holes which are to be through-plated have been drilled, the board can be plated, for example by panel plating, double-sided if desired, the plating having, as shown in FIG. 4, the same thickness in the hole [0014] 6 as on the surfaces 7 and 8. The thickness of the copper layer can in this connection be selected to be roughly 18-20 μm.
    [0015] After this, the pattern is laid out and the board is etched in a known manner, and FIG. 5 shows how the area closest to the drilled hole has been etched away and the hole [0015] 6 has been left with a plating 6 a to be soldered or to be connected to a conductor which may run at right angles to the plane of the paper.
    [0016] The invention is not limited to the exemplary embodiment shown in the drawings and explained in the description, but various modifications and variants are possible within the scope of the patent claims below. For example, the board does not have to be a multilayer board, but the invention can be applied to boards with a pattern on both sides or on only one side. It is of course also possible to apply the invention to laminates with carrier layers of a type other than glass fibre, for example ceramics, and the advantage is then that the surface roughness can be allowed to have values which are not usually permitted in the case of ceramic-based circuits. It is of course also possible to coat only certain portions of the carrier layer with the plane layer, namely those portions where either the surface roughness is greatest or the conductor width after etching is critically small. [0016]
    权利要求:
    Claims (6)
    [1" id="US-20010008680-A1-CLM-00001] 1. Printed circuit board made of laminate for electric circuits, comprising at least one carrier layer (1) and at least one surface layer (7) made of copper intended, after the removal of selected portions, for example by etching, to constitute the conductors on the board, characterized in that the surface roughness of the carrier layer has a coarseness of up to essentially the same size as the thickness of the copper layer, and in that, at least in the abovementioned portions, a surface-levelling plane layer (5 a, b) is arranged between the carrier layer (1) and the copper layer (7).
    [2" id="US-20010008680-A1-CLM-00002] 2. Printed circuit board according to
    claim 1 , characterized in that the plane layer consists of epoxy and has a thickness which is essentially the same size as the surface roughness of the carrier layer.
    [3" id="US-20010008680-A1-CLM-00003] 3. Printed circuit board according to either of the preceding claims, characterized in that the carrier layer contains glass fibre and epoxy, and in that the glass fibre content exceeds 70%.
    [4" id="US-20010008680-A1-CLM-00004] 4. Printed circuit board according to any one of the preceding claims, characterized in that the carrier layer has a surface roughness with an RA of up to ±10 μm.
    [5" id="US-20010008680-A1-CLM-00005] 5. Method for producing a printed circuit board laminate for electric circuits according to
    claim 1 , which laminate comprises a copper layer and a carrier layer with a surface roughness of essentially the same size as the thickness of the copper layer, characterized in that a layer (5 a, b) of liquid epoxy is applied to that surface or those surfaces of the carrier layer which in the end is or are to carry a copper layer, in that the epoxy layers are dried and hardened, and in that copper layers (7) are plated on top of the epoxy layers (5 a, b).
    [6" id="US-20010008680-A1-CLM-00006] 6. Method for producing printed circuit board laminate according to
    claim 5 , characterized in that through-holes (6), which are to be through-plated, are drilled after the epoxy layers (5 a, b) have been applied but before the copper layers are plated, so that the holes can be plated at the same time as the surface layers.
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    同族专利:
    公开号 | 公开日
    US6395378B2|2002-05-28|
    SE523150C2|2004-03-30|
    SE0000097L|2001-07-15|
    SE0000097D0|2000-01-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
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    US5799393A|1994-11-09|1998-09-01|Blaupunkt-Werke Gmbh|Method for producing a plated-through hole on a printed-circuit board|
    TW350194B|1994-11-30|1999-01-11|Mitsubishi Gas Chemical Co|Metal-foil-clad composite ceramic board and process for the production thereof the invention relates to the metal-foil-clad composite ceramic board and process for the production|
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    JP2003332752A|2002-05-14|2003-11-21|Shinko Electric Ind Co Ltd|Metal core substrate and its manufacturing method|
    US6801880B2|2002-07-02|2004-10-05|Dell Products L.P.|System and method for minimizing a loading effect of a via by tuning a cutout ratio|
    JP4291279B2|2005-01-26|2009-07-08|パナソニック株式会社|Flexible multilayer circuit board|
    JP2009518208A|2005-12-06|2009-05-07|イソラ−ユーエスエイ・コーポレーシヨン|Laminates for high-speed and high-frequency printed circuit boards|
    US10051746B2|2014-12-16|2018-08-14|Amphenol Corporation|High-speed interconnects for printed circuit boards|
    法律状态:
    2001-01-04| AS| Assignment|Owner name: TELEFONAKTIEBOLAGET LM ERICSSON, SWEDEN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BERGSTEDT, LEIF;LIGANDER, PER;REEL/FRAME:011420/0849 Effective date: 20001211 |
    2002-05-10| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2005-11-28| FPAY| Fee payment|Year of fee payment: 4 |
    2009-11-30| FPAY| Fee payment|Year of fee payment: 8 |
    2013-11-28| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    SE0000097A|SE523150C2|2000-01-14|2000-01-14|Circuit board and method for manufacturing circuit board with thin copper layer|
    SE0000097||2000-01-14||
    SE0000097-6||2000-01-14||
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